igital Systems Design 

Department of Electrical Engineering
ELEC261 – Digital Systems Design
Homework 3
1. Assuming that a VHDL code has been written to describe a 3-bit comparator
using the entity shown in Fig. 1.
Fig. 1
Using the ‘wait’ and ‘assertion’ statements, write the process(s) in the VHDL
testbench that use the following test cases and reports an error when the
outputs L, E and G are wrong at T = 9ns and T = 16ns.
A 0 7 4
B 0 3 7 2
5ns
The values in the waveforms are in decimal. Use binary values in
your testbench.
(5 marks)
2. Fig. 2 shows a sequential circuit.
J1
K1
J0
K0
Q0
Q0 Q1
Q1
Clear
Q
CLK
1
1
Fig. 2
(a) Copy Fig. 3 to your answer sheet and use it to illustrate the
waveforms of the outputs Q0, Q1 and Q. All used J-K flip-flops are
positive edge triggered.
A< B (L)
A= B (E)
A> B (G)
L A
3 E
B G
3
entity Comparator is
Port ( A, B: in std_logic_vector(2 downto 0);
L, E, G: out std_logic);
end Comparator;
Department of Electrical Engineering
Spring 2020 – FB
CLK
Q1
Q0
Q
Clear
1ns 5ns
Fig. 3
(5 marks)
(b) Use the structural design style to write the VHDL code (entity and
architecture) to describe the circuit in Fig. 2 if the entity of the J-K
flip-flop is as shown below:
entity JKFF is
port( Q, NQ: out std_logic;
CLK, CLR, J, K: in std_logic);
end JKFF;
(5 marks)